High voltage linear amplifier driving heavy capacitive loads with reduced power dissipation

ABSTRACT

A capacitive load drive circuit may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.

RELATED CASES

The present application is a divisional application of U.S. patentapplication Ser. No. 12/571,340, filed Sep. 30, 2009, now U.S. Pat. No.8,324,943, which in turn claims priority to U.S. Provisional ApplicationNo. 61/206,120, filed on Jan. 28, 2009, the disclosure of which ishereby incorporated by reference. This application is also related toU.S. patent application Ser. No. 12/571,352, filed on the same day asthe present application, entitled A STEPPED VOLTAGE DRIVE FOR DRIVINGCAPACITIVE LOADS, and assigned to the same assignee as the presentapplication, the disclosure of which is hereby incorporated byreference.

FIELD

The present invention relates to high voltage capacitive load drivingcircuits, which may be such as a piezoelectric transducer, and moreparticularly a matrix of piezoelectric transducers, such as may be usedin inkjet printer heads to actuate the production of an individual inkdroplet in the respective actuated ink jet droplet making mechanism inan inkjet head of an inkjet printer.

BACKGROUND

Heavy capacitive loads are very common in industrial and commercialsystems and equipment. A common example is a piezoelectric element whichis used extensively in such applications as ink jet printers, speakersand motor drives. A piezoelectric element, formed by piezoelectricmaterial sandwiched between two electrodes, is typically electricallymodeled as a large capacitor, with the piezoelectric material acting asboth a dielectric between the electrodes and an actuator under theinfluence of the electric field resulting from the application of avoltage across the electrodes. Indeed, an entire matrix of piezoelectricactuators for individual droplet making mechanisms in an inkjet printerhead may be modeled as a single capacitive load. Throughout thisapplication, unless otherwise expressly stated, discussion of acapacitive load in the form of a piezoelectric actuator will beunderstood to also include a matrix of such actuators producing a singlecapacitive load to which an output voltage is applied, and that thiscapacitive load also has typically resistive and inductive components toit.

The electrical drive to the capacitive load such as a piezoelectricactuator may be a controlled high voltage waveform delivered, as anexample, once per cycle of printer head operation or the like. Theshape, period and frequency of this waveform can be heavily dependentupon the application. Most piezoelectric element drive waveforms havefast switching transitions. There may also be a need for a portion ofthe waveform to exhibit finer linearity control and timing control, suchas when the droplet is actually formed in the output of the respectiveink jet printer ink jet nozzle and sized as it is ejected at a finelycontrolled time. Improvements in the ability to control these parametersare always in need to enhance such things as printer performance.

Therefore, typically a fast linear high voltage (HV) amplifier is usedto deliver the waveform to the piezoelectric element. In such a fastlinear high voltage (HV) amplifier, power dissipated while switching aload capacitor between a low voltage, such as a ground voltage GND(e.g., a zero voltage) to the high voltage VDD (as an example 50V) isgiven by:P _(diss) =C _(L) ×VDD ² ×·f  (1)where C_(L)=Load Capacitor capacitance, f=Frequency of drive waveform.

Existing linear capacitive load drives conform to equation 1. Thisrelationship can result in limitations on attributes of the applicationor engineering system, such as maximum load capacitance and frequency ofthe waveform. This relationship can further limit the number ofactuators that can be driven, such as in the piezoelectric inkjetprinter print head application, the number of inkjets and thereby theresolution of the printing by the print head, as well as the speed ofprinting, i.e., cycles per second of actuation. Achieving higherresolution and higher frequency of the drive voltage waveform isgenerally desirable. In inkjet printer piezoelectric applications,faster operation is always a goal resulting in faster printing speed.

FIG. 3 is an example of a conventional high capacitive load drivecircuit 140, utilizing a single amplifier, which may be like a PA78,PA79, PA86, PA69 or PA243 amplifier, available from applicants' assigneeCirrus Logic. The circuit 140 may have a class B gate drive amplifier142 utilized to drive a load capacitor 132 (“C_(LOAD)”), connected toground 170. The amplifier 142 may have a negative input 152, which isconnected to ground 170 through a resistor 156, such as a 1K ohmresistor and connected to the output through a resistor 169 such as a 9Kresistor. The amplifier 142 may have a positive input 150 connected toan input voltage 153, which may be an arbitrary drive voltage waveformwhich is, in turn, connected to ground 170.

The amplifier 142 may have a HiGate output 178 connected to the gate ofan external high power PFET 176, and a LoGate output 174 connected tothe gate of an external high power NFET 172. The amplifier 142 may beimplemented on an integrated circuit, and “external” means that the PFETand NFET may be, but need not necessarily be, implemented in a separateintegrated circuit and packaged separately (“external”) to the amplifier142, depending on the current drive required for the capacitive load.The source of the PFET 176 may be connected through a resistor 151, suchas a 0.1 ohm resistor, to a high voltage source 180, such as a 50 Vsource V50, in which the high voltage source 180 is, in turn connectedto ground 170. The source of the NFET 172 may be connected to ground 170through a resistor 171, such as a 0.01 ohm resistor for current sense.The drains of the PFET 176 and NFET 172 are connected to the loadcapacitor C_(LOAD) 132, such as a 527.4 nF capacitor. It will beunderstood that as high power integrated circuit technology advances, itmay become possible to integrate more of or even all of the circuitrydescribed in this application and related appropriate and necessarycircuitry on a single integrated circuit so that “external” power FETsand the like need no longer be “external.”

The output node of the amplifier connected to the load capacitor 132 mayalso be feed back to the negative input 152 of the amplifier 142 througha parallel RC arrangement containing a resistor 169, such as a 9 K ohmresistor and a capacitor 168, such as a 40 pF compensation capacitor, inparallel with resistor 169. The closed loop gain of the amplifier 142 isset by the resistive divider network comprised of resistors 169 and 156.

The amplifier 142 may have a +V_(S) connection 148 to a high voltagesupply 180, such as a 50 V supply, which voltage supply 180 is alsoconnected to ground 170. The voltage supply 180 is also connected to thesource of the PFET 176 through the resistor 151. The amplifier 142 mayalso have a connection 149 to a voltage supply 144, such as a 12 Vvoltage supply, also connected to ground 170 to set the gate drivevoltage. The amplifier 142 may also have a −V_(S) connection 143connected to ground 170 and a GND connection 145 connected to ground170, along with a V_(G) connection to a voltage supply 144, such as a 12V voltage supply also connected to ground 170.

In operation, the HiGate output 178 of the amplifier 142, in response tothe rising portion of the input 153, controls the voltage applied to thegate of the PFET 176 which controls the current flow through the PFET176 to the load capacitor 132 and, in response to the falling portion ofthe input voltage 153, controls the gate of the NFET 172 to regulate thecurrent flow from the C_(LOAD) capacitor 132 as the C_(LOAD) capacitor132 discharges to ground during a ramp down period. The load capacitorC_(LOAD) 132 thus charges up to from 0V to V_(S) (e.g., 50 V) during theramp up and discharges from 50V to 0V during the ramp down, assumingground is 0V.

The disadvantages to such operation with a single amplifier 142 are asnoted, namely, that the amplifier 142 exhibits high power dissipationand high cost. For piezoelectric inkjet printer applications, thisdisadvantage limits the resolution of printing and the speed ofprinting. Applicants have found that a better design according toaspects of the disclosed and present invention can reduce powerdissipation in the drive circuit and save cost for the application.

Adiabatic switching (between rail high or low voltage and the other railvoltage in sequential rails) has been employed in digital circuits atlow voltages as indicated in the following references. Indermaur et al.,Evaluation of Charge Recovery Circuits and Adiabatic Switching for LowPower CMOS Design, IEEE Symposium on Low Power Electronics (1994),relates to charge recovery through adiabatic switching for powerreduction in CMOS integrated circuits. Gabara, Pulsed Power SupplyCMOS—PPS CMOS, IEEE Symposium on Low Power Electronics (1994), relatesto similar ramped driving and charge recovery, called “pulsed power” inCMOS circuits. Similarly Svensson et al., Driving a Capacitive LoadWithout Dissipating fCV², IEEE Symposium on Low Power Electronics(1994), describes a similar “stepwise charging” in CMOS circuits.

FIG. 6 shows a schematic diagram of a circuit 310 useful inunderstanding energy dissipation while driving a capacitive loadC_(LOAD) 320. FIG. 6 shows two switches 322, 324 for charging anddischarging the capacitor C_(LOAD) 320. The circuit 310 includes avoltage supply 326, such as a 50 V DC power supply V_(DD), which whenvoltage controlled switch 322 is closed charges the load capacitor 320through a resistor 328 that is modeling the on resistance of switch 322,and a voltage controlled switch 324, which, when closed, discharges theload capacitor 320 through a resistor 330 to ground. Each of theswitches 322, 324 has a respective switch voltage supply 340, 342 toassist in the control of the timing and operation of the respectiveswitches.

FIG. 6 shows switch 322, that when closed charges the load capacitor 320with a charge Q=C_(LOAD)×V_(DD). The energy from the supply 326 toprovide this charge is E_(SUPPLY)=Q×V_(DD)=C_(LOAD)·V_(DD) ². The energystored in the capacitor 320 is E_(C)=C_(LOAD)×V_(DD) ²/2. These resultscan also be derived by integrating the instantaneous power over theperiod of interest.

$\begin{matrix}{E_{S\; U\; P\; P\; L\; Y} = {\int_{0}^{\infty}{{{i_{V\; D\; D}(t)} \cdot {V_{D\; D}(t)}}\ {\mathbb{d}t}}}} \\{= {C_{L} \cdot V_{D\; D} \cdot {\int_{0}^{\infty}\ \frac{{\mathbb{d}V_{O\; U\; T}} \cdot {\mathbb{d}t}}{\mathbb{d}t}}}} \\{= {C_{L} \cdot V_{D\; D} \cdot {\int_{0}^{50}{\mathbb{d}V_{O\; U\; T}}}}} \\{= {{C_{L} \times 50 \times 50} = {2500 \cdot C_{L}}}}\end{matrix}$ $\begin{matrix}{E_{C} = {\int_{0}^{\infty}{{i_{dd}(t)} \cdot {v_{out}(t)}\  \cdot {\mathbb{d}t}}}} \\{= {C_{L} \cdot {\int_{0}^{\infty}\ {\frac{\mathbb{d}{v_{O\; U\; T}(t)}}{\mathbb{d}t} \cdot {V_{OUT}(t)} \cdot {\mathbb{d}t}}}}} \\{= {{C_{L} \cdot \left\lbrack \frac{v_{O\; U\; T^{2}}}{2} \right\rbrack_{0}^{50}} = {1250 \cdot C_{L}}}}\end{matrix}$ E_(diss 1) = E_(S U P P L Y) − E_(C) = 1250 ⋅ C_(L)

This analysis shows that half of the energy supplied by the voltagesource is stored in the load capacitor while the other half isdissipated in switch 322 and resistor 328. During the discharge phasethe charge is removed from C_(LOAD) 320 and the energy is dissipated inswitch 324 and resistor 330. Thus the energy dissipated during eachswitching cycle is given by:E _(diss) =C _(LOAD) ·V _(DD) ²=2500·C _(LOAD)(V _(DD)=50 V)  Equ (1)

While existing systems are of great benefit, there is need to improveperformance of capacitive load drive systems, such as piezoelectricdrive systems, including through energy savings, improved speed ofoperation, and the ability to drive more load elements, such as morepiezoelectric elements. Advantageously the resolution of inkjet printerscan be improved according to aspects of embodiments of the presentinvention present invention.

SUMMARY

In one aspect, a high load drive circuit according to a possibleembodiment of the disclosed subject matter may comprise two amplifiers,such as a high current, high voltage gate drive amplifier for initialramp up and final ramp down for each cycle and a floating voltage linearoperational amplifier for finely tuning the transition at the top of thecycle waveform.

It will be understood that a capacitive load drive circuit is disclosedwhich may comprise a high current drive amplifier configured to becoupled to a capacitive load during a high current ramp up of thevoltage across the capacitive load to a cut off voltage; a low currentdrive amplifier configured to be connected to the capacitive load duringa low current ramp up of the voltage across the capacitive load, fromthe cut off voltage to a maximum voltage across the capacitive load; andthe high current drive amplifier configured to be connected to thecapacitive load during a high current ramp down of the voltage acrossthe capacitive load. The low current drive amplifier may be connected tothe capacitive load during a period of steady state of the voltageacross the capacitive load, intermediate the high current ramp up andthe high current ramp down. The low current drive amplifier may comprisean amplifier having a linear response in the range of the low currentramp up. The capacitive load may comprise a piezoelectric element, whichmay comprise an element of an ink jet printer head ink droplet producingmechanism. The low current drive amplifier may comprise a floating lowvoltage amplifier.

It will also be understood that a capacitive load drive circuit andmethod of load driving is disclosed which may be utilized in lieu of thehigh voltage/high current drive amplifier during the high current rampup and high current ramp down and may comprise a stepped voltage drivecircuit configured to cyclically charge a capacitive load to a selectedhigh voltage during a ramp up and configured to discharge the capacitiveload to a selected low voltage during a ramp down, which may comprise avoltage supply circuit comprising a circuit configured to sequentiallysupply to the load a variable voltage varying between each of aplurality of rails, each rail having a rail high voltage and a rail lowvoltage with the rail low voltage of the sequentially next railessentially equal to the rail high voltage of the sequentially precedingrail, during the ramp up, and configured to supply to the load avariable voltage varying between each of a plurality of rails, eachhaving a rail high voltage and a rail low voltage, with the rail highvoltage of the sequentially next rail essentially equal to the rail lowvoltage of the sequentially preceding rail during the ramp down.

In an illustrative embodiment, the rails may be equal and some fractionof a high voltage such as V_(DD)/n where n is the number of separaterails. The rails could be V_(DD)/n positive rails and V_(DD)/n negativerails, such as 0V−(+VDD/4), +V_(DD)/4−(+V_(DD)/2),+V_(DD)/2−(+3V_(DD)/4), (+3V_(DD)/4)−V_(DD) and −V_(DD)−(−3V_(DD)/4),−3V_(DD)/4−(−V_(DD)/2)−V_(DD)/2−(−V_(DD)/4) and −V_(DD)/4−0V assumingfour positive and four negative rails of equal difference between therail high voltage and the rail low voltage, i.e., V_(DD)/4.

The drive circuit could also comprise a multi-stage stacked chargingcircuit configured to be electrically connected to the capacitive loadand may comprise a first capacitor configured to be electricallyconnected to the capacitive load through a first switch during a firstcharging time period; a voltage supply configured to be electricallyconnected to the capacitive load through a second switch during a secondcharging time period; with the first capacitor configured to beelectrically connected to the capacitive load through the first switchduring a first discharging time period. The circuit may also comprise athird switch configured to electrically connect the capacitive load tothe selected low voltage during a second discharging time period.

The voltage supply circuit could comprise an n-stage stacked voltagesupply circuit, where n is an integer greater than or equal to 2, whichmay comprise n−1 capacitors and a voltage supply configured to each besequentially electrically connected to the capacitive load through arespective first through nth switch during a respective first throughnth charging time period; the n−1th capacitors configured to each besequentially electrically connected to the capacitive load in reverseorder during a first through n−1th discharging time period through therespective n−1th through first switches. The circuit may also comprisean n+1th switch configured to be electrically connected to thecapacitive load to the selected low voltage during an nth dischargingperiod. The drive circuit could comprise an amplifier selectivelyconnected across a plurality of n sequential intermediate rails eachwith a rail high voltage V₁ and a rail low voltage V₂ with respectiveselected ranges having an increasing value of V₁ during the ramp up andwith the respective ranges having a decreasing value of V₁ during theramp down, each defining an output range of the amplifier. The amplifiercould comprise an operational amplifier, and V₁-V₂ could be the same foreach respective rail. The rails can extend between a positive circuithigh voltage and a negative circuit low voltage. It will also beunderstood that the capacitive load drive circuit according to aspectsof an embodiment of the present invention may comprise a stepped voltagedrive circuit configured to cyclically charge a capacitive load to aselected high voltage during a high current ramp up and configured todischarge the capacitive load to a selected low voltage during a highcurrent ramp down, which may comprise: a voltage supply circuitcomprising a circuit configured to sequentially supply to the load avariable voltage varying between each of a plurality of rails, each railhaving a rail high voltage and a rail low voltage with the rail lowvoltage of the sequentially next rail essentially equal to the rail highvoltage of the sequentially preceding rail, during the high current rampup, and configured to supply to the load a variable voltage varyingbetween each of a plurality of rails, each having a rail high voltageand a rail low voltage, with the rail high voltage of the sequentiallynext rail essentially equal to the rail low voltage of the sequentiallypreceding rail during the high current ramp down; and may comprise a lowcurrent linear drive amplifier configured to be connected to thecapacitive load during a low current ramp up of the voltage to thecapacitive load, intermediate the high current ramp up and high currentramp down.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, functions, and advantages that are disclosed can beachieved independently in various embodiments of the present disclosureor may be combined in yet other embodiments, further details of whichcan be seen with reference to the following description and drawings,wherein like numerals depict like parts, and wherein:

FIG. 1 shows a schematic block diagram of a high capacitive load drivecircuit 20 according to aspects of an embodiment of the presentinvention;

FIG. 2 shows an example of a waveform used to drive capacitive loadssuch as piezoelectric elements in an inkjet printer head dropletproducing mechanism which applicants have used to simulate the operationof the circuit of FIG. 1;

FIG. 3 shows a schematic block diagram of an example of a conventionalhigh capacitive load drive circuit;

FIG. 4 shows a simulated wave form for the output of the circuit of FIG.1;

FIG. 5 shows schematically a transducer actuator for an ink dropletproducing mechanism as part of an ink jet printer head in an ink jetprinter according to aspects of an embodiment of the present invention;

FIG. 6 shows a conventional voltage drive circuit;

FIG. 7 shows a schematic circuit diagram of a drive circuit according toaspects of an embodiment of the present invention;

FIG. 8 shows schematically an example of a timing of the operation ofthe circuit of FIG. 7.

FIG. 9 shows a schematic circuit diagram of a drive circuit according toaspects of an embodiment of the present invention;

FIG. 10 shows an example of a simulation of the operation of the circuitof FIG. 9;

FIG. 11 shows a graph of normalized energy dissipation for given valuesof a step voltage; and

FIG. 12 shows in schematic and block diagram form a variable voltagestaged capacitive load drive circuit with a circuit such as isillustrated in FIG. 9 replacing an amplifier as illustrated in FIG. 1.

DETAILED DESCRIPTION

A novel linear amplifier drive according to aspects of the presentinvention can be utilized to reduce a substantial amount of powerdissipation in piezoelectric systems or like systems involving drivinglarge capacitive loads. As an example, aspects of the present inventioncan greatly improve performance of piezoelectric drive systems includingthrough energy savings, improved speed of operation, ability to drivemore piezoelectric elements, as an example allowing increased resolutionof inkjet printing and reduced costs. Also an improvement according toaspects of the present invention is the uniformity of the response ofthe overall drive circuit to the input, especially at the top of thecyclic driving waveform.

A simplified schematic block diagram shown in FIG. 1 is a highcapacitive load drive circuit 20 according to aspects of an embodimentof the present invention. The illustrative circuit 20 has two amplifiers22, 34 driving a load capacitor C_(L) 32, such as a 527.4 nF capacitor.Amplifier 22 may be a high voltage-high current output amplifier, suchas a class B, C or D gate driver amplifier, capable of driving largecurrents on the order of as an example 30-50 amps. The amplifier 22 isselected to be able to drive fast HV transitions and handle the highpeak currents, such as a model one of the Cirrus Logic amplifiers notedabove. Amplifier 34 may be a floating low voltage linear amplifier withlower current drive capability than amplifier 22 and at the same timehaving better linearity over its output voltage range.

Amplifier 34 may be selected to have a very linear output voltage in therange in which it is used to form part of the drive output voltagewaveform, such as is shown in FIG. 2 in each given actuation cycle,i.e., from the peak voltage generated by amplifier 22 to the peakvoltage of the entire drive circuit 20. Amplifier 34 thus acts as alinear amplifier for the slow transitions at high voltage with high gainaccuracy over a relatively shorter range of output voltages.

It will be understood by those skilled in the art, that this portion ofthe output voltage waveform is most important to delivering a finelytimed and tuned output of the drive circuit 20. In the example of anindividual ink jet printer head ink jet producing mechanismpiezoelectric actuator, a droplet of the right size and with the righttiming is very dependent on the accuracy of this portion of the drivecircuit output waveform. This aids in, among other things, the accuracyof the image being reproduced on the surface being printed upon by theinkjet printer. Those skilled in the art will understand that there areother applications for such a drive circuit.

The capacitive load driver circuit 20 can have high voltage/high currentamplifier 22, similar to or the same as the amplifier 142 of FIG. 3,connected between a voltage supply V_(S) 24, which may be at 40-50volts, as an example, and ground 26. This connection defines the rangeof the output of the amplifier 22. The output of the amplifier 22 may beconnected to the load capacitor 32 through a voltage controlled switch30 in the high current path to the load capacitor 32. This connection,through voltage controlled switch 30, as with amplifier 142 in FIG. 3connects a high voltage, such as a 40 V V_(S) when the HiGate output 52of the amplifier 22 is controlling the PFET 60 during a ramping upperiod as the drive circuit output waveform illustrated by way ofexample in FIG. 2 goes from a low voltage, such as 0V, to a highvoltage, such as V_(S) (e.g., 40 V) and connects to the load capacitanceC_(LOAD) 32. When the LowGate output 54 of the amplifier 22 iscontrolling the gate of the NFET 62 during the discharge of the loadcapacitor C_(LOAD) 32 from, as illustrated in FIG. 2, a high voltage ofV_(S), as an example, to a low voltage, such as ground 26, once again,while switch 30 is also closed.

The output node (“OUT2”) of the amplifier 22, connected to the loadcapacitor 32 may be fed back to the negative input 58 of the amplifier22, through an RC network containing a capacitor 66, such as a 40 pFcompensation capacitor, and a resistor 64, such as a 9K ohm resistor inorder to set closed loop gain.

The low voltage floating linear amplifier 34 may be connected through asimilar switch 36 to the load capacitor 32 in a low current path. Theamplifier 34 may be connected across a higher voltage supply 38(V_(S)+V_(DD)) through a V_(DD) connection 41 and supply voltage V_(S),through a V_(SS) connection 43, such as with V_(DD) equal to in therange of about ten volts or so, such that V_(S)+V_(DD) equals 50V in theexemplary circuit of FIG. 1 and 48V in the exemplary waveform of FIG. 2.This connection defines the range of output from the amplifier 34 tobetween V_(S) and V_(S)+V_(DD). A V_(S) level translator 40 may beconnected between a drive circuit input 50 and the positive input 62 ofamplifier 34, with the input 50 connected directly to the positive input56 of the amplifier 22. Voltage supply V_(S) may also be connected tothe negative input 60 of the amplifier 34 through resistor 64. Theoutput of the amplifier 34 may be fed back to the negative input 60 ofthe amplifier 34 through a resistor 66, such as a 1K resistor.

Amplifier 34 can operate as a floating low voltage linear operationalamplifier, using a floating V_(DD) supply (with respect to V_(S)) as apositive voltage supply. The return for amplifier 34 in the illustrativecircuit 20 is the high voltage supply Vs. The input to the floatingamplifier is level translated by the level translator block 40. Thetiming of the switches 30, 36 are controlled by the two comparators (notshown in the figure).

FIG. 2 shows an example of an ideal waveform used to drive capacitiveloads such as piezoelectric elements in an inkjet printer whichapplicants have used to simulate the operation of the circuit of FIG. 1.As shown in the FIG. 2, region 1 uses amplifier 22 as a switchingamplifier and drives peak current of 36 A for a 0.8 μF load for anexemplary 0.9 μs duration which defines a ramping up period from the lowvoltage of 0V to a high voltage of 40 V. During this ramp up phase inthe exemplary circuit of FIG. 1, the HiGate output 52 of the amplifier22 is controlling the current flow through the PFET 60 and the drain ofthe PFET 60 is connected to the load capacitance 32 through switch 30.

The simulation results for the exemplary circuit of FIG. 1 are shown inFIG. 4. The input to the amplifier 34 can be ramping up relativelyslowly during the illustrated period of time in FIG. 4 from about 5 μsto around 10 is, corresponding to the period 2 in the illustration ofFIG. 2. Thus, the output (“OUT1”) of the amplifier 34 ramps up from avoltage of V_(S) to approximately V_(S)+10V, while, as illustrated inFIG. 4, the input voltage on input 62 of the amplifier 34 is not rampingup between about 10 μs and about 14 μs, so that the output of amplifier34 does not increase during that period of time corresponding generallyto the period marked 2′ in FIG. 2.

Region 2 uses a floating linear amplifier 34 that drives 3.3 A ofcurrent in region 2 for the exemplary 1.94 μs. Switch 30 is open andswitch 36 is closed. The amplifier 34 is responding to an input onpositive input 62, which, as noted, may have a waveform as shown ascurve 90 in the simulated operating curves of FIG. 4, curve 92corresponding to the ramp up period of amplifier 22.

The drive circuit 20 in regions 3 and 4 goes back to switching amplifier22, with switch 36 open and switch 30 closed and drives peak current of37 A for 1.04 μs, including in region 3, a 0.17 μs period between a peakvoltage, shown as an example to be 48 V, and a lower voltage, e.g.,matching the peak voltage output of the amplifier 22 in region 1, i.e.,40 V, and a 0.87 μs period between 40 V and 0 V. With switch 30 closed,the amplifier 22 is controlling the discharge of the load capacitor 32to ground 26 through the NFET 62, by applying a variable voltage to thegate of the NFET 62. The discharge follows the simulation curve 92′ ofFIG. 4 in response to the input signal curve 90 shown in the simulationof FIG. 4, responsive to the input signal relatively rapidly rampingdown after about the 14 μs time until about the 19 μs time. The ramp upand ramp down times are different between the waveform in FIG. 2. andsimulated wave in FIG. 4. Thus, the peak currents drawn will bedifferent between FIG. 2 and FIG. 4 for the same capacitive load.

During the amplification carried out by amplifier 22 in region 2 of FIG.2 (between about 5 μs and 11 μs as illustrated in the simulation curvesshown in FIG. 4), very fine control can be exerted over and actuatorsuch as the piezoelectric unit 130 in FIG. 5, squeezing an ink drop outof an ink jet printer head in an ink jet printer head ink dropletproducing mechanism.

It will be understood that various ways may be utilized to control thetiming of the operation of certain aspects of the drive circuitaccording to embodiments of the present invention. For example, thecircuit could be controlled by switching control, such as, with voltagecontrolled switches, such as 30, 36 as discussed above. These switches30, 36 could be controlled by a controller (not shown) setting voltagesignals to the V+,V− terminals of the voltage controlled switches,according to some desired waveform similar to the ones illustrated asexamples in FIGS. 2 and 4. The specific timing and shape of thewaveforms as exemplified in FIGS. 2 and 4 depend heavily on theparticular application. As an example, the droplet producing mechanism120 illustrated schematically in FIG. 5 may need a rapid application ofpressure or force to the channel 124 to initiate droplet productionwithin some time for a cycle of the droplet production mechanism 120from producing a droplet to relaxing in preparation for a next dropletproduction, if necessary in the next inkjet printer head cycle. Thus,there exists the need for the rise in voltage applied to the load from 0to 40 V relatively rapidly.

The controller, under programmed control and with appropriate data andmemory, and in response to signals received as to the ink productionmechanisms that need to be actuated, cycle to cycle, the type of dropletproduction mechanism being used and the details of its actuation toproduce a droplet, and the like, can determine what the ramp up isneeded for the transient 0V-40V, and the voltage supply circuit isdriven accordingly.

With particular details being addressed, such as the size (and perhapseven the shape) and precise timing of production of a droplet in theexemplary application, and thus the needed application wave form for theactuator actuation, such as by piezoelectric actuator, the controllermay select such things as the voltage to which the low voltage floatinglinear amplifier will take its output, the ramp transient used (slope,shape, etc.). The controller may therefore be able to control the morefinely linear amplifier 34 in this region (2 in FIG. 2) to achieve thedesired results. The portion of the waveform where there is little or nochange of the output voltage from the amplifier 34 (region 2′ in FIG. 2)may be used to give the controller some flexibility as to high voltageselected and ramp used in region 2. That is, as an example, someflexibility in timing of the turn off of switch 36 and turn on of switch30, to begin the high current ramp down.

As illustrated in the simulation curves of FIG. 4, the low voltagefloating linear amplifier input signal could drive the voltage on theoutput OUT1 back to 40 V and the amplifier 22 could take over at thatpoint by closing switch 30 and opening switch 36.

Other various means of control are also possible. As an example, thetiming of the opening and closing of the switches 30, 36 may becontrolled by voltage comparators, such as the comparison of the voltageon OUT1 or OUT2 to some fixed or variable reference voltages, such asV_(S) or V_(DD) or other reference voltage(s) to control the switches30, 36. The voltage controlled switches 30 and 36 could respond to fixedinputs of variable voltage selected and timed to a particular waveformand cycle period, and always open and close switches 30, 36 at aparticular time relative to each other and the cycle time for theapplication, such as ink jet droplet generation.

Applicants have examined the energy drawn from voltage supply V_(S)E_(SUPPLY), with V_(S)=50 in the sample solution of FIG. 3. The valuefor V_(S) could be set to another value, such as 40V in the architectureshown in FIGS. 1 and 2. For the sample solution, energy stored incapacitor C_(L) 32=Ec, and energy dissipated E_(diss), which amounts toE_(SUPPLY)−E_(C). The following can be derived.

$\begin{matrix}{E_{S\; U\; P\; P\; L\; Y} = {\int_{0}^{\infty}{{{i_{V\; D\; D}(t)} \cdot {V_{D\; D}(t)}}\ {\mathbb{d}t}}}} \\{= {C_{L} \cdot V_{D\; D} \cdot {\int_{0}^{\infty}\ \frac{{\mathbb{d}V_{O\; U\; T}} \cdot {\mathbb{d}t}}{\mathbb{d}t}}}} \\{= {C_{L} \cdot V_{D\; D} \cdot {\int_{0}^{40}{\mathbb{d}V_{O\; U\; T}}}}} \\{= {{C_{L} \times 50 \times 40} = {2000 \cdot C_{L}}}}\end{matrix}$ $\begin{matrix}{E_{C} = {\int_{0}^{\infty}{{i_{dd}(t)} \cdot {v_{O\; U\; T}(t)}\  \cdot {\mathbb{d}t}}}} \\{= {C_{L} \cdot {\int_{0}^{\infty}\ {\frac{\mathbb{d}{v_{O\; U\; T}(t)}}{\mathbb{d}t} \cdot {v_{OUT}(t)} \cdot {\mathbb{d}t}}}}} \\{= {{C_{L} \cdot \left\lbrack \frac{v_{O\; U\; T^{2}}}{2} \right\rbrack_{0}^{40}} = {800 \cdot C_{L}}}}\end{matrix}$ E_(diss 1) = 1200 ⋅ C_(L)

Assuming a 40 V value for V_(S) and 10V for V_(DD) in the circuit ofFIG. 1, the following applies:

E_(diss 1) = 800 ⋅ C_(L)  since  E_(S U P P L Y) = 1600 × C_(L)  and  E_(C) = 800 × C_(L). In  regions  2  and  3, E_(diss 2) = E_(diss 3) = 48  C_(L), since$E_{S} = {{C_{L} \times 50 \times 8} = {{400\mspace{14mu} C_{L}\mspace{14mu}{and}\mspace{14mu} E_{C}} = {{C_{L} \cdot \left\lbrack \frac{v_{O\; U\; T^{2}}}{2} \right\rbrack_{40}^{48}} = {352 \cdot {C_{L}.}}}}}$

In region 4, E_(diss4)=1200×C_(L), as shown above for region 1. WithV_(DD)=40, E_(diss4)=800×C_(L), also as shown above.

Therefore, E_(diss)×(V_(DD)=50V)=2496×·C_(L), for a single amplifierusing a single V_(S) equals 50 V voltage supply of FIG. 3, andE_(diss)×(V_(DD)=40V)=1696×C_(L) for the two amplifier arrangement ofFIG. 1. According to aspects of an embodiment of the present invention,an improvement of 32% (reduction) in the amount of energy dissipated isachieved. The architecture for the capacitive load drive circuit of FIG.1 was modeled against a circuit with the single class B gate driver asillustrated in FIG. 3, with high gain and low gain outputs connected tothe gates of an external PFET and external NFET respectively and theload connected to the drains of the PFET and NFET in the conventionalmanner illustrated in FIG. 3. The simulation was for a 50 V linearamplifier driving a 0.527 μF load capacitor.

The amplifier used according to an aspect of an embodiment of thepresent invention has the following differences or advantages overtraditional class G amplifiers. Class G amplifiers have global feedbackto maintain linearity over the entire voltage range. In the intendedapplication for the amplifier circuit 20 according to the presentinvention, linearity is not required over the entire voltage range.Hence, only amplifier 22 will require feedback while amplifier 34 can bea class D switching amplifier. Class G amplifiers also typically have asingle output stage capable of driving the load current in, e.g., apiezoelectric application, where load current is high during fastswitching and it is low during slow linear transitions. Only amplifier22, therefore, needs to drive high currents.

The simulation was performed with respect to comparing the prior artsingle 50 V class B high voltage linear amplifier system driving to apeak 50 V and returning to 0 V per cycle, driving a 0.527 μf capacitiveload, with a rise from 0 V to around 40 V over about a 5 μs period, arise from around 40 V to about 50 V over an approximately 4 μs period,steady state for about a 5.5 μs period followed by a reduction in outputvoltage from 50 V to 0 V over about a 5.5 μs period. The average currentdrawn was found to be 3.56 A and power dissipation 178 W.

Using a circuit according to an embodiment of the present invention,with the same load tied to the outputs of two amplifiers 22, 34, asdescribed above, the transients shown in FIG. 4 were modeled andsimulated, and the average current drawn from the floating 10 V supplywas found to be 0.437 A and power dissipation of 4.37 W. At the sametime, the average current for a 40 V high voltage linear amplifier wasshown to be 2.5 A, resulting in a 100 W power dissipation.

Therefore, the difference in power dissipation is between 178 W in theprior art circuit and 104.37 W, i.e., a 41% difference. This matchesclosely with the theoretical 32% energy dissipation reduction notedabove.

It will be understood by those skilled in the art that “high” capacitiveloads vary with a given application and that the difference between thevoltage and current that can be handled by the “high voltage, highcurrent operational amplifier” 22 vis-à-vis the floating low voltagelinear amplifier 34 also varies with application. As used herein, thoseskilled in the art will understand high and low to be distinctive of theoperation of the high voltage/high current amplifier 22 in thoseapplications requiring relatively high current to the load over arelatively short period of time during a ramp up of, as an example, thecharging of a relatively large capacitive load, and the similarrelatively large and rapid current flow from the load, such as todischarge the capacitive load during a steep ramp down period. This isas opposed to a relatively slower transient at the top of the drivecircuit waveform from a starting voltage (generally at the voltage atwhich the high voltage/high current amplifier left off), to a maximumvoltage relatively closed to the starting voltage for the lowvoltage/low current amplifier 34. Examples here have been given circuitswhere “high” voltage is 40-50 V and high current is in the range of tensof amps. The voltage and current ranges in which the exemplary lowcurrent/low voltage portions of the circuits described herein operateare on the order of 8-10 V and 3-5 amps. The high voltage/high currentamplifiers currently on the market can handle much higher voltage, onthe order of hundreds of volts and tens of amps. For purposes of thisapplication, however, the difference between “high” and “low” means thatthe “low” value of voltage or current is in a range of about 0.1-20% ofthe high value, and most often 0.1-10%.

It will be understood that a high capacitive load drive circuit fordriving external capacitive loads is disclosed which may comprise a highcurrent drive amplifier, such as amplifier 22 of FIG. 1 configured to becoupled to a capacitive load during a high current ramp up of thevoltage across the capacitive load to a cut off voltage, such as theperiod/portion 1 of time in FIG. 2 and the ramp up transient labeled as92 in FIG. 4. A low current drive amplifier, such as amplifier 34 inFIG. 1, may be configured to be connected to the capacitive load duringa low current ramp up of the voltage across the capacitive load, fromthe cut off voltage to a maximum voltage across the capacitive load,such as the ramp up illustrated during the period 2 in FIG. 2 and theramp up time period of curve 94 in FIG. 4. The high current driveamplifier may be configured to be connected to the capacitive loadduring a high current ramp down of the voltage across the capacitiveload, such as the time periods 3 and 4 in FIG. 2 and the ramp down curve92′ in FIG. 4. The low current drive amplifier may be connected to thecapacitive load during a period of steady state of the voltage acrossthe capacitive load, intermediate the low current ramp up and the highcurrent ramp down, such as the period labeled 2′ in FIG. 2. During thisperiod, the output signal connected to the capacitive load may requirehigh gain accuracy and hence linearity. The low current drive amplifiermay comprise an amplifier having a linear response in the range of thelow current ramp up, such as between a cut off voltage for the highcurrent ramp up, for example, 40 V and 48V. The capacitive load maycomprise a piezoelectric element, which may comprise an element of anink jet printer head ink droplet producing mechanism such as is shownschematically in FIG. 5.

FIG. 7 shows a schematic circuit diagram of a capacitive load drivecircuit 310′ having a multi-supply arrangement, in the specific example,a two stage stepped voltage supply. The circuit 310′ contains theelements of the circuit 310 of FIG. 6 for charging C_(LOAD) 320 toV_(DD) during the ramp up and discharged during ramp down. In a steppedvoltage drive with n steps, such as n=2 as illustrated in FIG. 2, therecan be a number (n) of intermediate rails with specific voltage levelsbetween the rails, which may be, but need not necessarily be equal, asin the example where the incremental values are equal to V_(DD)/n. Inaddition there can be a number (n) of switches controlling current flow,as an example for either the charging or discharging of the load, as thecase may be, during such charging and discharging of the capacitor 320by (V_(DD)·C_(LOAD)) amounts.

In addition to the elements of FIG. 7, the circuit 310′ of FIG. 7contains, by way of example, a current supply, which may comprise acharge storage device, such as capacitor C_(BIG) 354. The capacitor 354may be connected to the load capacitor 320 through a resistor 352 whichmodels the ON resistance of the switch when switch 350 is closed. Thetiming of the closing of switch 350 may be done by a voltage supply 356,which may provide a time varying closure signal, such as a saw toothtime varying signal to the V+ and V− terminals of the voltage controlledswitch 350.

FIG. 8 illustrates an output voltage waveform 360 for the circuit 310′of FIG. 3 illustrating a timing of operation of the circuit. The controlof the timing of the closing of the switches 322, 324 and 350 by therespective switch control signals 342,340 and 356 can be set up so thatduring a first charging time period switch 350 is closed and a portion362 of the output waveform 360 of the voltage supply circuit 310′ isgenerated during a first charging time period as illustrated in FIG. 8.In an exemplary embodiment, where the output waveform serves to charge acapacitive load, such as actuation of a piezoelectric element, theportion 362 of the output waveform 360 initiates the actuation of thepiezoelectric element 130 shown in FIG. 5. Also in an exemplaryembodiment, this can begin to squeeze a channel 124 (or the liquid in achannel 124) in an inkjet printer inkjet droplet producing mechanism120, or a nozzle 122 in such a channel 124, to begin to force out inkfrom the individual inkjet nozzle 122 in an inkjet printer print head(not shown). During the first charging time period 362, the outputwaveform can provide an output voltage varying from 0 to V_(DD)/2, whichin the exemplary embodiment is the value of the voltage on C_(BIG) 354.

Thereafter, with switch 324 closed, and switch 322 having been reopened(it being understood that throughout this application, unless expresslynoted otherwise, all other switches, including ones previously noted asbeing closed, remain open while the switches under discussion areclosed) the voltage supply V_(DD) is connected to the load, and in theexemplary embodiment a capacitive load such as a piezoelectric elementin an inkjet printer print head, increases the output voltage applied tothe load C_(LOAD) from V_(DD)/2 to V_(DD) during a second charging timeperiod 364. During a subsequent time period 366 the output voltage maybe maintained at V_(DD). Thereafter, with switch 350 closed, the chargestorage element, such as capacitor C_(BIG) 354 may be charged toV_(DD)/2 from the charge storage device C_(LOAD) 320 during a firstdischarging time period 368, wherein the load goes from V_(DD) toV_(DD)/2. In other words, the charge that was initially provided by theV_(DD)/2 supply during ramp up is dumped back into C_(BIG) 354.

In the exemplary embodiment, this reduction in voltage applied to theload can begin to relax the piezoelectric element 130 squeeze on thechannel 124 (or the liquid in the channel 124) in an inkjet printer inkdroplet producing mechanism 120, by relaxing the deformation thepiezoelectric element or transducer 130 under the influence of theelectric field created by the voltage across the electrodes of thepiezoelectric element 130, to begin to draw ink into the individualinkjet nozzle channel 124 from a reservoir (not shown) in an inkjetprinter print head (not shown), through an ink supply line 126. It willbe understood that other means may be used, alone or in combination withsuch relaxation of the piezoelectric element to resupply the channel 124of the given nozzle 122, such as a pressure applied to the reservoir(not shown).

Finally, switch 322 may be closed to connect the load 320 to groundthereby discharging the load capacitor C_(LOAD) 320 through switch 322and resistor 328 during a second discharging time period 370 and theoutput waveform thus provides an output voltage varying from V_(DD)/2 to0. In the exemplary embodiment, the reduction in voltage to the load cancompletely relax the piezoelectric element 130 pressure exerted on inkin the inkjet channel in preparation for a subsequent actuation of thepiezoelectric element 130 at a later time by the application of anotheroutput voltage waveform 360 to the load.

The following analysis of energy dissipation E_(diss) during suchcharging of the load 320 applies with the switch 350 closed.

$\begin{matrix}{{E_{C\; B\; I\; G} - {\int_{0}^{\infty}{{{i_{C\; B\; I\; G}(t)} \cdot {v_{C\; B\; I\; G}(t)}}\ {\mathbb{d}t}}}} = {C_{L} \cdot \frac{V_{DD}}{2} \cdot {\int_{0}^{\infty}\ \frac{{\mathbb{d}V_{OUT}} \cdot {\mathbb{d}t}}{\mathbb{d}t}}}} \\{= {C_{L} \cdot \frac{V_{DD}}{2} \cdot {\int_{0}^{\frac{V_{D\; D}}{2}}{\mathbb{d}V_{OUT}}}}} \\{= {{C_{L} \times \frac{V_{DD}}{2} \times \frac{V_{DD}}{2}} = {25^{2} \cdot C_{L}}}}\end{matrix}$ $\begin{matrix}{E_{C\;{Load}} = {\int_{0}^{\infty}{{i_{C\;{Load}}(t)} \cdot {v_{OUT}(t)} \cdot \ {\mathbb{d}t}}}} \\{= {C_{L} \cdot {\int_{0}^{\infty}\ {\frac{\mathbb{d}{V_{OUT}(t)}}{\mathbb{d}t} \cdot {v_{O\; U\; T}(t)} \cdot {\mathbb{d}t}}}}} \\{= {{C_{L} \cdot \left\lbrack \frac{V_{O\; U\; T^{2}}}{2} \right\rbrack_{0}^{\frac{V_{DD}}{2}}} = {\frac{25^{2}}{2} \cdot C_{L}}}}\end{matrix}$$E_{{diss}\; 1} = {{E_{CBIG} - E_{C\;{Load}}} = {\frac{25^{2}}{2} \cdot C_{L}}}$

It will be understood that, with the intermediate voltage set to anarbitrary voltage V₁ between V and V_(DD), E_(diss1) will equal(C_(L)×V₁ ²)/2.

Later, with switch 324 closed, during the charging from V₁ to V_(DD),i.e., from V_(DD)/2 to V_(DD), where V₁=V_(DD)/2, the following applies:

$\begin{matrix}{E_{S\; U\; P\; P\; L\; Y} = {\int_{0}^{\infty}{{{i_{V\; D\; D}(t)} \cdot {V_{D\; D}(t)}}\ {\mathbb{d}t}}}} \\{= {C_{L} \cdot V_{D\; D} \cdot {\int_{0}^{\infty}\ \frac{{\mathbb{d}V_{O\; U\; T}} \cdot {\mathbb{d}t}}{\mathbb{d}t}}}} \\{= {C_{L} \cdot V_{D\; D} \cdot {\int_{25}^{50}{\mathbb{d}V_{O\; U\; T}}}}} \\{= {C_{L} \times 50 \times 25}}\end{matrix}$ $\begin{matrix}{E_{C} = {\int_{0}^{\infty}{{i_{dd}(t)} \cdot {v_{O\; U\; T}(t)}\  \cdot {\mathbb{d}t}}}} \\{= {C_{L} \cdot {\int_{0}^{\infty}\ {\frac{\mathbb{d}{v_{O\; U\; T}(t)}}{\mathbb{d}t} \cdot {v_{OUT}(t)} \cdot {\mathbb{d}t}}}}} \\{= {{C_{L} \cdot \left\lbrack \frac{v_{O\; U\; T^{2}}}{2} \right\rbrack_{25}^{50}} = {C_{L} \cdot \left\lbrack {\frac{50^{2}}{2} - \frac{25^{2}}{2}} \right\rbrack}}}\end{matrix}$$E_{{diss}\; 2} = {{E_{SUPPLY} - E_{C}} = {\frac{25^{2}}{2} \cdot C_{L}}}$

The total energy dissipated for the 0−V_(DD) transition is:E _(diss) _(—) _(RampUp) =E _(diss1) +E _(diss2)=25² ×C _(LOAD)  Equ (2)

It will be seen that the energy dissipated in a discharging transitionof the load from V_(DD)−0 E_(diss) _(—) _(RampDwn) will also equal25²×C_(LOAD).

The total energy dissipated during one switching cycle therefore is:E _(diss2)=2×25² ×C _(LOAD)  Equ (3)

Comparing equations 1 (provided above in the “Background” section) and 3one can conclude that the energy savings factor with a two stage voltagedrive as opposed to a one stage voltage drive is equal to 2. In asimilar fashion it can be shown that in theory energy dissipated for ann-step voltage drive during one switching cycle is:E _(diss) _(—) _(n) =n×(V _(DD) /n)² ×C _(LOAD)  Equ (4)

The energy savings factor for an n-step drive is given by:

$\begin{matrix}{S_{n} = {\frac{V_{{DD}^{2}} \cdot C_{LOAD}}{\left\lbrack {C_{LOAD} \cdot \frac{V_{{DD}^{2}}}{n^{2}} \cdot n} \right\rbrack} = n}} & {{Equ}\mspace{14mu}(5)}\end{matrix}$

With the intermediate voltage set to the arbitrary V₁, E_(diss2) willequal C_(LOAD)·[V₁ ²+(V_(DD)−V₁)²] and the total energy dissipated willequal E_(diss1)+E_(diss2) and the normalized total dissipationE_(diss<n>) will be [V₁ ²+(V_(DD)−V₁)²]/V_(DD) ² which forms theparabola shown in FIG. 11, which can be utilized to select optimalvalues for the voltage steps, in an adiabatically driven output voltage,such as, for driving high capacitive loads in piezoelectric driveactuators in ink jet printer head droplet production mechanisms. Forexample on the left side of the curve the normalized energy dissipationdrops significantly down to about 10 or so steps and then more or lesslevels off so that the problems (such as greater complexity ofcircuitry), overtake any advantage in continued reductions in energydissipation at smaller incremental changes.

In FIG. 9 there is shown a multi-supply capacitive load drive circuit380, which may include an output connected to a load, such as acapacitive load C_(LOAD) 320 such as a 0.8 μF capacitance. The circuit380 may include a multi-supply stacked (stepped) voltage supply to theload 320, which may comprise a switch 382, which when closed connects acapacitor 382C to the load 320 through a resistor 382R. The stackedsupply 380 may further include a switch 384, through which a capacitor384C is connected to the load 320 through a resistor 384R. In similarfashion the remaining stages including switch 386, capacitor 386C andresistor 386R, switch 388, capacitor 388C and resistor 388R, switch 390,capacitor 390C, resistor 390R, switch 392, capacitor 392C and resistor392R, switch 394, capacitor 394C and resistor 394R, switch 396,capacitor 396C and resistor 396R, switch 398, capacitor 398C andresistor 398R, may serve to connect the respective capacitors to theoutput and thus to the load 320.

A switch 400, when closed, may serve to connect a high voltage, such asV_(DD) 326, to the load 320 through a resistor 400R. A further switch402 may serve to connect the load to ground through a resistor 402R.

In operation, as simulated in FIG. 10 the switches 382, 384, 386, 388,390, 392, 394, 396, 398 and 400 may be sequentially closed to step thevoltage at the output (“OUT”) by selected sequential amounts, such asregular intervals of, by way of example, 5 V intervals, for an exemplaryten stage/step circuit with V_(DD) equal to 50 V. It will be understoodthat the steps need not be identical rail to rail, such as, each being aspecific fraction of V_(DD), such as V_(DD)/n, as in the Example of FIG.9.

As shown in FIG. 10 this sequentially switching in of differentcapacitive elements, applies at the output, and thus to the load 320,increasing voltage steps from 0−V_(DD), in the exemplary embodiment, 10steps of voltage output varying in 5 V intervals from 0−V_(DD). As withthe exemplary two stage circuit of FIG. 2, the source of the current tothe load, applied in an exemplary embodiment in charging a capacitiveload, is the high voltage source V_(DD). The remaining voltage sourcesare formed in the exemplary embodiment by the respective capacitors382C, 384C, 386C, 388C, 390C, 392C, 394C, 396C and 398C. This increasein voltage to the load during each of a respective ten successivecharging time periods with all but the tenth charging time periodcausing the output to provide current flow to the load 320 from arespective charge storage device 382C, 384C, 386C, 388C, 390C, 392C,394C, 396C and 398C. The tenth charging time period results in currentflow generated by applying the voltage source V_(DD) to the load 320.

Also as illustrated in the simulated waveform of FIG. 10, in adischarging sequence, each of the switches 398, 396, 394, 392, 390, 388,386, 384 and 382 are sequentially closed, in that order, in theexemplary embodiment, charging the respective capacitors 398C, 396C,394C, 392C, 390C, 388C, 386C, 384C and 382C in decreasing amounts, as anexample, in 5 V intervals, from V_(DD)−5 to V_(DD)−45, with theexemplary ten stage circuit and V_(DD)=50, and equally sized decrements.Finally switch 402 is closed taking the output and the voltage acrossthe load 320 from V_(DD)−45 to 0 in the exemplary embodiment. It will beunderstood that as used herein, ground is simply a common voltage belowV_(DD) and need not be zero volts and could even be a negative voltage.

The simulation of FIG. 10 compares a waveform 312′ for a single stage 50V V_(DD) supply as exemplified by the circuit of FIG. 6 to the simulatedwaveform 312 created during the simulation of the operation of thecircuit of FIG. 9.

In generating FIG. 10, a simulation of the circuit of FIG. 9 was modeledto simulate a 10 step voltage drive for a 50 V switched driving a loadequal to a 0.8 μF capacitive load. The large capacitors for the 5 Vsteps C5V-C45V, are the capacitors 382C, 384C, 386C, 388C, 390C, 392C,394C, 396C and 398C and were assumed to be 1 F for simulation purposesonly. The nodes 5V-45V, corresponding to capacitors 382C, 384C, 386C,388C, 390C, 392C, 394C, 396C and 398C, in that order, were initializedto the corresponding voltage using an .ic statement in a Spicesimulator. The switches 382, 384, 386, 388, 390, 392, 394, 396, 398, 400and 402 were assumed to be ideal switches.

The results of this simulation were compared with a single 50 V steplinear drive to determine energy savings. Current through the load 320was simulated for the sequential closure of each of the switches 382,384, 386, 388, 390, 392, 394, 396, 398, 400 and 402 during therespective charging time periods shown in FIG. 10, and charge recoveryfor each of the capacitors 398C, 396C, 394C, 392C, 390C, 388C, 386C,384C and 382C was also simulated for each of the respective dischargingtime periods associated with the closure sequentially of the switches398, 396, 394, 392, 390, 388, 386, 384, 382 and 402 in that order. Theaverage power dissipation can be approximated by looking at the energylost by the 50 V supply with ground return since there is no chargerecovery for the 50 V supply.

For a single stage voltage supply also simulated, the average currentdrawn was 2.667 amps. The average power dissipation was 133.35 W. Thesimulation also showed that the current drawn from the 50 V V_(DD)supply was 0.628 amps and power dissipation was 13.4 W, which matchesvery closely with the theoretical power dissipation savings for an nstage supply circuit with n=10 as equaling 133.35/13.4=9.95, which isvery nearly equal to n=10.

Those skilled in the art will understand that voltage drive circuit,such as a capacitive load drive circuit and method of operation of thesame is disclosed and may include a multi-stage stacked charging circuitsuch as the circuit of FIG. 7, electrically connected to the capacitiveload 20, which may include a first capacitor, such as the capacitorC_(BIG) 354, electrically connected to the capacitive load 320 through afirst switch 350 during a first charging time period, i.e., chargingtime period 362 of waveform 360 as shown in FIG. 8. The circuit may alsoinclude a voltage supply, such as V_(DD) 326 electrically connected tothe capacitive load 320 through a second switch 324 during a secondcharging time period 364 as shown in FIG. 8. The first capacitor 354 maybe electrically connected to the capacitive load 320 through the firstswitch 350 during a first discharging time period 368 as illustrated inFIG. 8.

The system and method in an exemplary embodiment may comprise a thirdswitch 322 electrically connecting the capacitive load 320 to groundduring a second discharging time period 370 as illustrated in FIG. 8.The capacitive load 320 may comprise a piezoelectric element 130, suchas illustrated in FIG. 5 which may comprise an inkjet printer head inkdroplet production mechanism 120 inkjet actuator 130.

The system and method by way of an exemplary embodiment may comprise ann-stage stacked charging circuit such as the ten stage circuit of FIG.9, which may comprise n−1 capacitors, and a voltage supply, by way ofexample the nine capacitors 382C, 384C, 386C, 388C, 390C, 392C, 394C,396C and 398C and a voltage supply V_(DD), each electrically connectedin sequence to the capacitive load 320 through a respective firstthrough nth switch, such as switches 382, 384, 386, 388, 390, 392, 394,396, 398 and 400 during a respective first through nth charging timeperiod, such as is illustrated by way of example in FIG. 10 for therespective closure of the switches 382, 384, 386, 388, 390, 392, 394,396, 398 and 400; the n−1th capacitors 398C, 396C, 394C, 392C, 390C,388C, 386C, 384C and 382C may each be sequentially electricallyconnected to the capacitive load 320 in reverse order during a firstthrough n−1th discharging time periods through the respective n−1ththrough first switches, as illustrated in FIG. 9 for the discharge timeperiods associated with the closure of each switch 398, 396, 394, 392,390, 388, 386, 384 and 382 sequentially.

The system and method may comprise an n+1th switch, such as, switch 402,electrically connecting the capacitive load to ground during an nthdischarging period as is also illustrated in FIG. 10. The capacitiveload 320 may comprise a piezoelectric element, such as piezoelectrictransducer 130 illustrated by way of example in FIG. 5, which maycomprise an inkjet printer head 120 inkjet droplet production mechanismactuator.

FIG. 5 illustrates schematically the principal elements of a printerhead ink droplet production mechanism 120, such as in an inkjet printerhead (not shown), with which the present invention may be used. Theinkjet printer head ink droplet production mechanism 120 typicallyincludes a nozzle 122 fed by a feed channel 124, which may receive inkfrom a supply reservoir (not shown) through an ink supply passage 126. Apiezoelectric transducer 130, which may be the capacitive load 320illustrated in FIGS. 6, 7 and 9, or a part of that load, may beconnected to the output of a drive circuit, such as those illustrated inFIG. 6, 7 or 9 by a voltage supply connector 132 and to ground by aconnector 134, appearing, as noted above, as a high capacitance load tothe drive circuits as shown in FIG. 6, 7 or 9.

It will also be understood that the drive circuit 310 or 380 or the likecan be employed with the low current linear amplifier 34 such asillustrated in FIG. 1, to generate the high current ramp up and highcurrent ramp down portions of the cyclical wave form of the drivecircuit output, to provide a relatively linear ramp up and a relativelylinear ramp down. Such a circuit is illustrated by way of example inFIG. 12. In FIG. 12, there is shown a multi-supply capacitive load drivecircuit 420, with the circuit 380 of FIG. 9 in place of the amplifier 22in FIG. 1, connected to the capacitive load 32 through a switch 30during ramp up and ramp down. The circuit as explained in regard to FIG.9 selectively sequentially connects ground and then the capacitors 382C,384C, 386C, 388C, 390C, 392C, 394C, 396C and 398C, and then voltagesupply V_(S) to the capacitive load 32 increasing the voltage on theload in 5V increments from 0 volts to 50 volts. Subsequently, afteramplifier 34 has been connected to the capacitive load 32 through switch36, switch 36 is opened and switch 30 is again closed and the voltage onthe capacitive load 32 sequentially charges the capacitors 382C, 384C,386C, 388C, 390C, 392C, 394C, 396C and 398C in reverse order during aramp down, with the ramp down being completed by switch 402 being closedto connect the load 32 to ground.

It will be understood that in a portion of the drive circuit output tothe capacitive load, such as an ink droplet production mechanismactuator, linearity is not at a premium, and the savings in powerdissipation may overcome any lack of linearity. Using the samequantitative techniques shown above, the energy dissipated using drivecircuit 380 in FIG. 9 in place of amplifier 20 in FIG. 1 can be derivedas 256×C_(L). The energy savings in comparison to exemplary existingsolution of FIG. 3. is 89.75%.

In operation, the transducer 130 deforms as voltage is applied acrossthe connectors 132 and 134 and either bends or bulges in the directionof the channel 124 or bulges out on both sides, including in thedirection of the channel 124, serving to squeeze a droplet of ink out ofthe nozzle each time the transducer is so actuated. In some printerheads, the relaxation of the transducer, as voltage is removed, may alsoserve to suck ink into the channel 124 through the supply line 126. Itwill be understood also that the piezoelectric transducer 130 may forceink out of the ink jet droplet producing mechanism 120 by other means,such as squeezing the channel 124 or the nozzle 122 or both, and morethan one piezoelectric element 130 may be used per droplet productionmechanism 120.

Distinct from the adiabatic computing circuits, embodiments of thepresent invention including adiabatic stepping and voltage controlcircuits are used to control the output of a high capacitive load drivercircuit such as a step voltage amplifier by defining the output rangefor each step. Also distinct from adiabatic computing circuits,embodiments of the present invention are for an analog application witha portion or all of the output waveform requiring gain and linearity.Creating a floating rail according to aspects of embodiments of thepresent invention provides several advantages. In certain embodiments,there can be created an inductor based floating rail. Circuits accordingto aspects of embodiments of the present invention can generate a rampthat drives a drive circuit amplifier based upon the signal level, i.e.,output signal range of the amplifier.

It should be apparent that the scope and content of the presentdisclosure are not limited to the above embodiments but should beconsidered in scope and content taking into account the manner in whichthe disclosed embodiments may be changed and modified without departingfrom the scope and spirit of the disclosed subject matter and claims,some of which changes and modifications have been noted above.

We claim:
 1. A capacitive load drive circuit comprising: a steppedvoltage drive circuit configured to cyclically charge a capacitive loadto a selected high voltage during a high current ramp up and configuredto discharge the capacitive load to a selected low voltage during a highcurrent ramp down, comprising: a voltage supply circuit configured tosupply to the capacitive load a variable voltage through sequentiallyelectrically connected rails, with the rail voltage of the sequentiallynext rail higher than the rail voltage of the sequentially precedingrail, during the high current ramp up, the rails being configured toeach be electrically connected to the capacitive load in reverse orderduring the high current ramp down; and a low current linear driveamplifier configured to be connected to the capacitive load during a lowcurrent ramp up, intermediate the high current ramp up and high currentramp down.
 2. The capacitive load drive circuit of claim 1 wherein thevoltage supply circuit comprises: a multi-stage stacked charging circuitconfigured to be electrically connected to the capacitive loadcomprising: a first capacitor configured to be electrically connected tothe capacitive load through a first switch during a first ramp upcharging time period of the high current ramp up; a voltage supplyconfigured to be electrically connected to the capacitive load through asecond switch during a second ramp up charging time period of the highcurrent ramp up; and the first capacitor configured to be electricallyconnected to the capacitive load through the first switch during a firstramp down discharging time period of the high current ramp down.
 3. Thecapacitive load drive circuit of claim 2, said voltage supply circuitfurther comprising: a third switch configured to electrically connectthe capacitive load to the selected low voltage during a second rampdown discharging time period of the high current ramp down.
 4. Thecapacitive load drive circuit of claim 1 wherein the voltage supplycircuit comprises an n-stage stacked voltage supply circuit comprising:n−1 capacitors and a voltage supply configured to each be sequentiallyelectrically connected to the capacitive load through a respective firstthrough nth switch during a respective first through nth ramp upcharging time period of the high current ramp up wherein the n−1thcapacitors configured to each be sequentially electrically connected tothe capacitive load in reverse order during a first through n−1th rampdown discharging time period of the high current ramp down through therespective n−1th through first switches.
 5. The capacitive load drivecircuit of claim 4 further comprising: an n+1th switch configured toelectrically connect the capacitive load to the selected low voltageduring an nth discharging period of the high current ramp down.
 6. Thecapacitive load drive circuit of claim 1, wherein the capacitive loadcomprises a piezoelectric element.
 7. The capacitive load drive circuitof claim 6, wherein the piezoelectric element comprises an element of anink jet print head ink droplet producing mechanism.
 8. The capacitiveload drive circuit of claim 1, wherein the low current linear driveamplifier comprises a floating low voltage amplifier.
 9. The capacitiveload drive circuit of claim 1, wherein the low current linear driveamplifier is contained in one or more integrated circuits.
 10. A methodof driving a capacitive load comprising: utilizing a stepped voltagedrive circuit to cyclically charge the capacitive load to a selectedhigh voltage during a high current ramp up and to discharge thecapacitive load to a selected low voltage during a high current rampdown, comprising: utilizing a voltage supply circuit to supply to thecapacitive load a variable voltage through sequentially connected rails,with the rail voltage of the sequentially next rail higher than the railvoltage of the sequentially preceding rail, during the high current rampup, and to electrically connect the rails to the capacitive load in areverse order during the high current ramp down; and, utilizing a lowcurrent linear drive amplifier configured to be connected to thecapacitive load during a low current ramp up, intermediate the highcurrent ramp up and high current ramp down.
 11. The method of claim 10further comprising: allowing for a period of steady state of the voltageacross the capacitive load, intermediate the high current ramp up andthe high current ramp down.
 12. The method of claim 10, wherein thecapacitive load comprises a piezoelectric element.
 13. The method ofclaim 12, wherein the piezoelectric element comprises an element of anink jet print head ink droplet producing mechanism.
 14. The method ofclaim 10, wherein the low current linear drive amplifier comprises afloating low voltage amplifier.
 15. The method of claim 10, wherein thelow current linear drive amplifier is contained in one or moreintegrated circuits.